1. Field of the Invention
The present invention relates to a fully differential amplification device that has a common mode feedback circuit and is capable of improving the stability of the initial operation.
2. Prior Art
In recent years, in communication circuits, mixed signal circuits and the like, a fully differential amplification device that has two terminals for each of input and output and is completely symmetrical in circuit arrangement has been more frequently used from the viewpoint of removing high frequency noise and digital noise from the power source, the ground (GND) and the like. The fully differential amplification device in which the DC voltage (common voltage) of the output is not readily determined requires common mode feedback.
FIG. 5 shows an example of the structure of a conventional fully differential amplification device. In a differential amplifier 3, a positive input signal Vinp is inputted to a positive input terminal 1, and a negative input signal Vinn is inputted to a negative input terminal 2. The differential amplifier 3 generates a positive output signal Voutp1 and a negative output signal Voutn1 from a positive output terminal 21 and a negative output terminal 22, respectively. The positive output signal Voutp1 and the negative output signal Voutn1 of the differential amplifier 3 are inputted to a common voltage generation circuit 4.
The common voltage generation circuit 4 generates the output common voltage of the differential amplifier 3 based on the positive output signal Voutp1 and the negative output signal Voutn1 of the differential amplifier (operational amplifier) 3. An output common voltage 41 of the differential amplifier 3 which is the output of the common voltage generation circuit 4 is inputted to an inverting input terminal of a common mode feedback comparator 7. A reference voltage 5 is inputted to a noninverting input terminal of the common mode feedback comparator 7. Reference numeral 6 represents the ground (GND).
The common mode feedback comparator 7 compares the output common voltage 41 of the differential amplifier 3 with the reference voltage 5, and feeds back a common mode feedback signal 8 representative of the result of the comparison, to a common mode feedback terminal 44 of the differential amplifier 3 to thereby cause the differential amplifier 3 to operate so that the output common voltage 41 of the differential amplifier 3 coincides with the reference voltage 5.
FIG. 6 shows a concrete example of the circuit of the fully differential amplification device having common mode feedback. In FIG. 6, the positive input signal Vinp is inputted from the positive input terminal 1, and the negative input signal Vinn is inputted to the negative input terminal 2.
The differential amplifier 3 includes: MOS transistors M1 and M2 constituting a differential transistor pair; a MOS transistor M3 serving as a common current source that feeds a differential amplification current to the MOS transistors M1 and M2; and MOS transistors M4 and M5 constituting load current sources that individually feeds current to the MOS transistors M1 and M2. The positive input terminal 1 is connected to the gate of the MOS transistor M1, and the negative input terminal 2 is connected to the gate of the MOS transistor M2. The sources of the MOS transistors M1 and M2 are commonly connected, and connected to the drain of the MOS transistor M3. The source of the MOS transistor M3 is connected to the ground 6. The drains of the MOS transistors M1 and M2 are connected to the drains of the MOS transistors M4 and M5, respectively. The sources of the MOS transistors M4 and M5 are connected to the power source 12, and the gates thereof are commonly connected.
The positive input signal Vinp and the negative input signal Vinn are amplified by the differential amplifier 3 having the above-described structure, and the positive output signal Voutp1 and the negative output signal Voutn1 are outputted from the positive output terminal 21 and the negative output terminal 22 provided at the drains of the MOS transistors M2 and M1, respectively, The positive output signal Voutp1 and the negative output signal Voutn1 outputted from the differential amplifier 3 are inputted to the output common voltage generation circuit 4.
The output common voltage generation circuit 4 includes inversion amplification MOS transistors M10 and M11, MOS transistors M8 and M9 serving as the current source, and voltage arithmetic averaging resistors R1 and R2. The drains of the MOS transistors M10 and M11 are connected to the drains of the MOS transistors M8 and M9, respectively. The sources of the MOS transistors M8 and M9 are connected to the ground 6. The sources of the MOS transistors M10 and M11 are connected to the power source 12. A series circuit of the resistors R1 and R2 are connected between the drains of the MOS transistors M10 and M11, and the connecting point of the resistors R1 and R2 is the output terminal of the output common voltage generation circuit 4 for outputting the output common voltage 41. A positive output terminal 42 and a negative output terminal 43 are provided at the drains of the MOS transistors M10 and M11. A positive amplification output signal Voutp which is the positive output signal Voutp1 inversion-amplified by the MOS transistor M11 is outputted from the positive output terminal 42. A negative amplification output signal Voutn which is the negative output signal. Voutn1 inversion-amplified by the MOS transistor M11 is outputted from the negative output terminal 43.
When the positive output signal Voutp1 and the negative output signal Voutn1 outputted from the differential amplifier 3 are inputted to the output common voltage generation circuit 4 having the above-described structure, the positive output signal Voutp1 and the negative output signal Voutn1 are inversion-amplified by the MOS transistors M10 and M11, and at the same time, arithmetically averaged by the resistors R1 and R2, whereby the output common voltage 41 is generated. The output common voltage 41 is inputted to the common mode feedback comparator 7, the output common voltage 41 is compared with the reference voltage 5, and the common mode feedback signal 8 which is the comparison result signal is fed back to the differential amplifier 3.
The common mode feedback comparator 7 includes: MOS transistors M14 and M15 constituting a comparison transistor pair; a MOS transistor M13 serving as the current source that feeds a comparison current to the MOS transistors M14 and M15; and MOS transistors M16 and M17 serving as the load on the MOS transistors M14 and M15. The sources of the MOS transistors M14 and M15 are commonly connected, and connected to the drain of the MOS transistor M13. The source of the MOS transistor M13 is connected to the ground 6. The drains of the MOS transistors M14 and M15 are connected to the drains of the MOS transistors M16 and M17. The sources of the MOS transistors M16 and M17 are connected to the power source 12, and the gates thereof are connected to the drains thereof, respectively. The drain (gate) of the MOS transistor M16 serves as the output terminal for the common mode feedback signal 8, and is connected to the common gate of the MOS transistors M4 and M5 of the differential amplifier 3. The MOS transistor M16 and the MOS transistors M4 and M5 constitute a current mirror circuit. The output common voltage 41 is inputted to the gate of the MOS transistor M14, and the reference voltage 5 is inputted to the gate of the MOS transistor M15.
The output common voltage 41 is compared with the reference voltage 5 by the common mode feedback comparator 7 having the above-described structure.
When the output common voltage 41 is higher than the reference voltage 5, the current of the MOS transistor M13 flows through the MOS transistors M14 and M16, the drain voltage of the MOS transistor M16 decreases, and the gate voltage of the MOS transistor M16 decreases. Consequently, the gate voltages of the MOS transistors M4 and M5 which are the load current source of the differential amplifier 3 decrease to increase the source-gate voltages of the MOS transistors M4 and M5. Thereby, the currents of the MOS transistors M4 and M5 increase, and the drain voltages of the MOS transistors M4 and M5 increase. For this reason, the gate voltages of the MOS transistors M10 and M11 increase, the currents of the MOS transistors M10 and M11 decrease, and the drain voltages of the MOS transistors M10 and M11 decrease. Consequently, the output common voltage 41 decreases.
When the output common voltage 41 is lower than the reference voltage 5, since the current of the MOS transistor M13 flows through the MOS transistors M15 and M17, the drain voltage of the MOS transistor M16 increases, and the gate voltage of the MOS transistor M16 increases. Consequently, the gate voltages of the MOS transistors M4 and M5 increase to decrease the source-gate voltages of the MOS transistors M4 and M5. Thereby, the currents of the MOS transistors M4 and M5 decrease, and the drain voltages of the MOS transistors M4 and M5 decrease. For this reason, the gate voltages of the MOS transistors M10 and M11 decrease, the drain currents of the MOS transistors M10 and M11 increase, and the drain voltages of the MOS transistors M10 and M11 increase. Consequently, the output common voltage 41 increases.
After all, feedback is made so that the output common voltage 41 is the same as the reference voltage 5, so that the output common voltage 41 becomes the same as the reference voltage 5.
A current source circuit 10 includes a current source 11 and a MOS transistor M18. The current source 11 has one end connected to the power source 12 and its other end connected to the drain and gate of the MOS transistor M18. The source of the MOS transistor M18 is connected to the ground 6. The MOS transistor M18, together with the MOS transistors M3, M8, M9 and M13, constitutes a current mirror circuit. As described above, the MOS transistor M3 constitutes the current source of the differential amplifier 3 including the MOS transistors M1 and M2, the MOS transistors M8 and M9 constitute the current source of the inversion amplification MOS transistors M10 and M11, and the MOS transistor M13 constitutes the current source of the common mode feedback comparator 7.
There is a problem in that at the startup of the power source, at the time of switching of the mode (for example, at the time of switching of the levels of the input signal) and the like, the output voltage of the differential amplifier 3 is frequently fixed not at the desired reference voltage but at a different voltage such as the ground (GND) or the power supply voltage (VDD).
FIG. 8 shows the circuit of an amplifier using an operational amplifier, or a high-pass filter in which such a problem readily occurs in FIG. 8, reference numerals 31 and 32 represent capacitors, and reference numerals 33 to 36 represent resistors. When the capacitance of the capacitors 31 and 32 is C1, the resistance value of the resistors 33 and 34 is R3, and the resistance value of the resistors 35 and 36 is R4 in FIG. 8, the transfer function H(s) of the input and output isH(s)=R4/R3*{s/(s+1/(C1*R3))}
(Here, s=jω),
so that a high-pass filter is constituted in which the gain of the passband is R4/R3 and the cutoff angular frequency is ωc=1/(C1*R3). For this reason, no DC voltage is transmitted. Therefore, it is necessary for the input DC voltage to be supplied by the output common voltage.
At that time, if the stabilization point of the common voltage is at a voltage other than the desired common voltage, for example, the ground (GND), the stabilization point of the common voltage is fixed at that voltage, so that amplification cannot be performed.
As another example, an inverting amplifier including resistors and an operational amplifier is shown in FIG. 9. In FIG. 9, reference numerals 33 to 36 represent resistors. When the resistance value of the resistors 33 and 34 is R3 and the resistance value of the resistors 35 and 36 is R4 in FIG. 9, an inverting amplifier with a gain R4/R3 is constituted. When the input DC voltage is VIN and the output DC voltage is VO, the input terminal DC voltage V1 of the operational amplifier isV1=V IN*R4/(R3+R4)+VO*R3/(R3+R4).Therefore, when the output of the inverting amplifier is other than the desired common voltage and the DC voltage V1 is outside the input dynamic range of the operational amplifier, the operating point is shifted, so that there are cases where amplification cannot be performed. In addition, when the input DC voltage VIN transitionally becomes the ground GND or the power supply voltage VDD at the time of switching of the mode and the like and the resistively divided voltage V1 is outside the input dynamic range, the input and output voltages of the operational amplifier are fixed at other than the desired operating point, so that normal amplification cannot be performed.
FIG. 10 shows a current/voltage conversion circuit using an operational amplifier. The input of this current/voltage conversion circuit is current sources 13 and 14, and by the currents of the current sources 13 and 14 flowing through the resistors 35 and 36, the voltage outputs 21 and 22 are taken out. When the common voltage of the reference voltage 5 is VCOM, Voutn=VCOM−Iinp*R4. When Iinp=0, the input and output voltages of the operational amplifier are VCOM, and in this case, if the common voltage is not correctly supplied, normal amplification cannot be performed, either.
For this reason, for example, when the input voltage is outside the dynamic range of the differential amplifier 3, a second comparator is provided, and auxiliary current is fed until the output voltage is within the dynamic range (see Japanese Unexamined Patent Application Publication No. 2000-323940).
FIG. 7 shows a concrete example thereof. In FIG. 7, reference numeral 100 represents the above-mentioned second comparator. The comparator 100 includes comparison MOS transistors M21 to M24 and a MOS transistor M20 serving as the current source. The sources of the MOS transistors M21 to M24 are commonly connected, and connected to the drain of the MOS transistor M20. The source of the MOS transistor M20 is connected to the ground 6. The negative input signal Vinn is applied to the gate of the MOS transistor M21, the positive input signal Vinp is applied to the gate of the MOS transistor M22, and a comparison reference voltage 200 is applied to the gates of the MOS transistors M23 and M24. The drains of the MOS transistors M21 and M22 are connected to the power source 12, the drain of the MOS transistor M23 is connected to the gate of the MOS transistor M10, and the drain of the MOS transistor M24 is connected to the gate of the MOS transistor M11. Except the above, the structure is similar to that of FIG. 6.
In the fully differential amplification device structured as described above, when the input DC voltage is as low as not more than the input dynamic range, if the circuit including the MOS transistors M20 to M24 is absent, the MOS transistors M1 and M2 are disabled, and when the drain currents of the MOS transistors M4 and M5 flow through the parasitic capacitances of the gates of the MOS transistors M10 and M11, the drain voltages of the MOS transistors M4 and M5 increase, so that the gate voltages of the MOS transistors M10 and M11 increase. Consequently, there are cases where the MOS transistors M10 and M11 are disabled, the drain voltages of the MOS transistors M10 and M11 decrease to a low voltage and the output common voltage is fixed at the low voltage.
This condition continues, for example, until the input DC voltage gradually increases into the input dynamic range after power-on and the MOS transistors M1 and M2 start to operate.
That is, the drain currents of the MOS transistors M4 and M5 flow through the parasitic capacitances of the gates of the MOS transistors M10 and M11 to increase the gate voltages of the MOS transistors M10 and M11, and shortly, the MOS transistors M10 and M11 are disabled. Therefore, the drain voltages of the MOS transistors M10 and M11 also decrease, no current flows through the MOS transistor M14 the drain voltage and gate voltage of the MOS transistor M16 increase, the MOS transistors M16, M4 and M5 are also disabled, and no current flows through the MOS transistors M4 and M5 either. However, the charges stored in the gate capacitances of the MOS transistors M10 and M11 are held, so that the MOS transistors M10 and M11 continue to be disabled. For this reason, the drain voltages of the MOS transistors M10 and M11 are held at the low voltage, and consequently, the output common voltage is fixed at the low voltage.
Therefore, the comparator 100 including an auxiliary current source of the MOS transistor M20 and the MOS transistors M21 to M24 is added, and when the input voltages (Vinp, Vinn) are lower than the comparison reference voltage 200, the current of the MOS transistor M20 serving as the current source flows through the MOS transistors M23 and M24 to decrease the gate voltages of the MOS transistors M10 and M11. Consequently, the drain voltages of the MOS transistors M10 and M11 increase, and the current of the MOS transistor M13 of the common mode feedback comparator 7 flows through the MOS transistors M14 and M16 to decrease the drain voltage and gate voltage of the MOS transistor M16 and decrease the gate voltages of the MOS transistors M4 and M5. If the currents of the MOS transistors M23 and M24 are higher than the drain currents of the MOS transistors M4 and M5, the output common voltage 41 is not fixed at the low voltage.
After power-on, the input DC level gradually increases, and when it becomes within a predetermined dynamic ranger the transistors M1 and M2 can perform amplification. For this reason, when the input voltage increases into the predetermined dynamic range, since the input voltage is higher than the comparison reference voltage 200, the current of the MOS transistor M20 flows to the power source 12 by way of the MOS transistors M21 and M22. Thereafter, the normal common mode feedback operation is performed, and the normal operation is performed.
Conventionally, there are cases where at the startup of the power source, at the time of switching of the mode and the like, the common mode feedback operation of the differential amplifier does not work normally, the stabilization point is other than the desired common voltage such as the power source or the ground (GND), and the operation is converged to other than the desired common voltage. For this reason, for example, as shown in Japanese Unexamined Patent Application Publication No. 2000-323940, when the input voltage is other than the dynamic range of the differential amplifier (operational amplifier), the new comparator 100 that detects whether the input voltage is within the dynamic range or not is provided, and by using the result of the comparison, auxiliary current for startup is fed.
Now, description will be given again with reference to FIG. 7 showing the conventional example. Although the input is Pch transistors in the example of Japanese Unexamined Patent Application Publication No. 2000-323940, for comparison with the present invention, description will be given as a differential amplifier in which the input differential transistors are Nch transistors. In Japanese Unexamined Patent Application Publication No. 2000-323940, there are cases where when the input voltage is outside the dynamic range, that is, when it is low enough to disable the MOS transistors M1 and M2, if the MOS transistors M4 and M5 are enabled, the MOS transistors M10 and M11 are disabled and this fixes the output common voltage 41 at the low voltage. For this reason, the new comparator 100 is provided that includes the MOS transistors M20 to M24 and compares the input dynamic range. When the input voltage is a low voltage that is outside the input dynamic range, the input voltage is lower than the comparison reference voltage 200, and the current of the MOS transistor M20 is fed to the positive output terminal 21 and the negative output terminal 22 of the differential amplifier 3, that is, to the gates of the inversion amplification MOS transistors M10 and M11 in the output common voltage generation circuit 4 by way of the MOS transistors M23 and M24 so as to increase the output common voltage 41 of the fully differential operational amplifier 3. When the input voltage is within the dynamic range, since the input voltage is higher than the comparison reference voltage 200, the current of the MOS transistor M20 is fed to the power source 12 through the MOS transistors M21 and M22.
However, when the input voltage is outside the dynamic range and lower than the reference voltage 200, the current of the MOS transistor M20 flows through the MOS transistors M23 and M24 and in order that the drain currents of the MOS transistors M23 and M24 can enable the MOS transistors M10 and M11, the transitional currents of the MOS transistors M23 and M24 in the condition where the input voltage is lower than the comparison reference voltage 200 are necessarily fed in a larger amount than the transitional currents of the MOS transistors M4 and M5. For this reason, a large amount of current is necessarily used for startup. In addition, the current is necessarily fed to the power source as useless current after normal startup.
Moreover, since the gates of the startup MOS transistors M21 and M22 are connected to the input in addition to the differential amplification transistors, the unnecessary parasitic capacitances by the MOS transistors M21 and M22 are added to the input, so that the frequency characteristic is deteriorated.
Moreover, in order that the comparator 100 operates normally, it is necessary that The reference voltage 200 be higher than a voltage which is the sum of the gate-source voltages of the MOS transistors M23 and M24 and an overdrive voltage of the MOS transistor M20, that is, a voltage which is the difference when a threshold voltage Vth is subtracted from the gate-source voltage Vgs20 of the MOS transistor M20. Moreover, to completely switch the comparator 100, it is necessary that the input voltage be higher than a voltage which is the sum of the reference voltage 200 and the overdrive voltages of the MOS transistors M21 and M22 multiplied by √{square root over ( )}2. For this reason, for example, when the lower limit voltage of the input is 1V (the overdrive voltage {Vgs3−Vth} of the MOS transistor M3+the gate-source voltages Vgs1 of the MOS transistors M1 and M2) and the overdrive voltages of the MOS transistors M21 to M24 are 0.2 V, it is necessary that the reference voltage 200 be approximately 1.3 V so that the comparator 100 is completely switched.
When setting is made like this, the lower limit voltage of the input is approximately 1.6 V since it is necessary to completely switch the comparator 100. As a consequence, by the addition of the comparator 100, the lower limit voltage of the input is significantly reduced from 1.0 V to 1.6 V, and the input dynamic range is reduced. With the process becoming finer recently, from the limitation of the withstand voltage, for example in the 0.18 micron process, the standard power supply voltage is 1.8 V, and it is difficult to structure an amplifier with measures Like those of the conventional example. Moreover, to reduce the overdrive voltage, it is necessary to increase the size of the transistors, and the increase in size as well as the increase in the number of transistors of the comparator increases the chip area.